1. Field of the Invention
The present invention relates to photodetector arrays intended to be used as image sensors in imaging devices such as, for example, video cameras or digital photographic devices. More specifically, the present invention relates to such arrays made in monolithic form.
2. Discussion of the Related Art
FIG. 1 illustrates a circuit diagram of a portion of an elementary cell 1 of a photodetector array. Cell 1 includes a photodiode D having its anode connected to a low reference supply line VSS. The cathode of diode D is connected to a precharge and detection terminal K. Terminal K is connected to a high supply line VDD via a precharge MOS transistor 3 having its gate receiving a precharge control signal RESET. Terminal K is also connected to the gate of a MOS transfer transistor 5 interposed between high power supply VDD and the drain of a read control transistor 7. The source of transistor 7 forms output terminal OUT of cell 1 and its gate receives a read control signal READ.
A technology in which at least transistors 3, 5, and 7 of cell 1 are formed in an integrated circuit coated with metallization levels, photodiode D being formed above the last metallization level, is considered in the present description.
FIG. 2 partially and schematically illustrates a known integration mode of some of the elements of FIG. 1.
Transistors 3 and 5 are formed in a semiconductor substrate 10, typically single-crystal silicon, generally of type P. More specifically, each transistor 3, 5 is formed in an active area of substrate 10 defined, for example, by insulating trenches 11. For each transistor 3, 5, a channel region, defined by a respective insulated gate 12 laid on substrate 10, separates N-type source/drain regions 14 formed in substrate 10. Above substrate 10 are superposed intermediary metallization levels generally referred to as IML. Levels IML comprise metallizations embedded in at least one insulating material and intended, in particular, to form terminal K and transfer a contact in the form of a metal plate 18 from a last metallization level to above an upper insulating layer 16.
A cathode 20 of a photodiode D encapsulates plate 18. Cathode 20 results from a low-temperature deposition, on the order of 2000° C. Cathode 20 is, for example, made of N-type doped amorphous silicon. The cathode 20 of each photodiode D is individualized and separate from the cathodes of the photodiodes of the neighboring cells. The anode of diode D is common to several photodiodes, generally at least to all photodiodes in a row or column of the array. The common anode is formed of a stacking of an undoped amorphous silicon layer 22 and of a P-type doped upper layer 24. Layer 24 is covered with a transparent ITO-type metal layer 26 intended, for example, to be connected to low power supply VSS.
A disadvantage of the preceding structure is the fact that the restored image exhibits white points or darkness defects. Such a malfunction is linked to the creation of leakage currents between regions 20 and 22, especially when the distance between cathodes is reduced and the cathodes are at their maximum biasing level, generally ranging between 1.5 and 2 V.
To overcome such malfunctions, and thus suppress short-circuits, it has been provided to increase the dimensions of the interval separating two cathodes with respect to their minimum values determined by the electric and geometric characteristics (doping and thicknesses) of the electrodes. This solution is contrary to the general goal of increasing the number of cells formed in a given integration surface.